1. Field of the Invention
This present invention relates to a semiconductor device having a side wall insulating film and a manufacturing method thereof.
2. Description of the Related Art
Recently, as a semiconductor chip is downsized, it is getting more and more difficult to form a shallow extension portion and highly activate impurities injected into a gate electrode. In order to solve the trade-off problem of the forming the shallow extension portion and the highly activating impurities, a manufacturing method of forming the extension layer after forming diffusion layers that are used as a source or drain layer is proposed.
However, as shown in FIG. 14, a width Y of a side wall insulating film 125 may be wider than a width X′ of a groove 120 due to a process dispersion, even though it is desirable that the width Y′ of the side wall insulating film 125 is equal to the width X′ of the groove 120 or shorter. In other words, the side wall insulating film 125 may extend on diffusion layers 119 that are used as a source or drain layer.
As a result, a performance of a MOS transistor 122 shown in FIG. 14 may be degraded because a space where a silicide layer 126b formed on the diffusion layer 119 is contact with a contact plug 127 is smaller. And also, a contact resistance may be greater because the space is smaller. In addition to that, this may cause the MOS transistor to unable to be downsized because a distance D (shown in FIG. 14) between a contact portion (bottom portion) of the contact plug 127 and a side surface of a gate electrode 114 is shorter. A semiconductor device having a side wall insulating film is also disclosed in Japanese Laid open kokai 2000-58816 and U.S. Pat. No. 6,624,034.
On the other hand, as shown in FIG. 10, a side wall insulating film 125 may be formed on a diffusion layer 119, and a bottom area Sc′ of the contact plug 127 is decreased, thereby increasing a contact resistance between the diffusion layer 119 and the contact plug 127.